In modern electronic circuits, electrostatic discharge (“ESD”) protection is an important feature for the protection of internal circuitry on semiconductor devices e.g., integrated circuits). ESD may be characterized by fast transient high voltage discharges resulting from two objects at different potentials coming in contact with each other, or when a high electrostatic field develops between two objects in close proximity. An ESD event in an integrated circuit (IC) may be caused by static electricity generated by a user, equipment handling the IC, power supply voltage transients, circuit testing, and the like. An ESD event may create a sufficiently high voltage to cause a destructive breakdown of transistor devices or components connected to the inputs or outputs of the integrated circuits. ESD is one of the major causes of device failure in the semiconductor industry.
FIG. 1 illustrates a conventional high voltage ESD protection circuit 100, which includes a single high voltage NPN ESD clamp 110, bond pad 140, and ground 150. NPN ESD clamp 110 includes an NPN transistor 120 and a resistor 130. The base of NPN transistor 120 and the emitter of NPN transistor 120 are connected by resistor 130. The NPN clamp 110 is coupled between bond pad 140 and ground 150 in that the collector of NPN transistor 120 is coupled to the bond pad 140 and the emitter of NPN transistor 120 is coupled to ground 150. The resistor 130 may be a large value resistor to eliminate spurious behavior during normal operation of NPN transistor 120.
In operation, IC designers generally achieve ESD protection by relying on the collector breakdown of the high voltage NPN ESD clamp 110 to turn on NPN transistor 120. This will cause NPN transistor 120 to clamp into its low resistive state at a voltage between Vbceo and Vbces.
Some high voltage circuits may be protected by a clamp with a single NPN transistor 110 as shown in FIG. 1. Other circuits may require a multiple stacked NPN ESD clamps. For example, a second high voltage NPN ESD clamp 115 is illustrated by FIG. 2. FIG. 2 illustrates a conventional high voltage ESD protection circuit 200, which includes a second NPN ESD clamp 115 connected in series with NPN ESD clamp 110 and between bond pad 140 and ground 150. The second NPN ESD clamp 115 includes transistor 125 and resistor 135 configured as before with NPN ESD clamp 110. Examples of circuits that may require multiple ESD clamps connected in series include supply rails or high voltage semiconductor devices used to level shift and drive thin film transistors (TFT) found on LCD panels.
For high voltage circuits, it is difficult to make ESD clamps that consume a small amount of die area. The clamps often need to be stacked, as shown in FIG. 2. In order to maintain the same path resistance, it is required to double the clamps in both parallel and in series. Therefore, in order to maintain the same ESD performance, four such cells are required. As a result, conventional high voltage NPN ESD transistor clamps 110, 115 consume a substantial amount of silicon area. The high voltage rating forces large lateral spacing rules, and the collector diffusion is lightly doped and therefore highly resistive, which further increases the footprint. For example, a twelve-channel TFT level shifter implemented in a high performance IC process with a double stacked 60V ESD cell may consume approximately 40,000 um2 . Embodiments of the present invention may reduce the required silicon area and cost of ESD protection in comparison with the existing NPN clamps of FIGS. 1 and 2. Additionally, embodiments of the present invention may electrically outperform their predecessors.